diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
index 498cf7f..f059db5 100644
--- a/board/delta/lowlevel_init.S
+++ b/board/delta/lowlevel_init.S
@@ -1,10 +1,5 @@
 /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
+ * (C) Copyright 2006 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,14 +26,6 @@
 
 DRAM_SIZE:  .long   CFG_DRAM_SIZE
 
-/* wait for coprocessor write complete */
-.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-.endm
-
-
 .macro wait time
 	ldr		r2, =OSCR
 	mov		r3, #0
@@ -49,13 +36,9 @@
 	bls		0b
 .endm
 
-/*
- *	Memory setup
- */
-
 .globl lowlevel_init
 lowlevel_init:
-	/* Set up GPIO pins first ----------------------------------------- */
+	/* Set up GPIO pins first */
 	mov	 r10, lr
 
 	/*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
@@ -73,22 +56,7 @@
 	bic		r1, r1, #0x80000000
 	str		r1, [r0]
 
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface					    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
-	/*	   clocks to settle. Only necessary after hard reset...	    */
-	/*	   FIXME: can be optimized later			    */
-	/* ---------------------------------------------------------------- */
-;	wait #300
-
 mem_init:
-
-#define NEW_SDRAM_INIT 1
-#ifdef NEW_SDRAM_INIT
-
 	/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
 	ldr		r0, =ACCR
 	ldr		r1, [r0]
@@ -99,7 +67,7 @@
 	/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
 	ldr		r0, =MDCNFG
 	ldr		r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
-	/*	ldr		r1, =0x80000403 */
+	/* ldr		r1, =0x80000403 */
 	str		r1, [r0]
 	ldr		r1, [r0]	/* delay until written */
 
@@ -140,121 +108,6 @@
 	orr		r1, r1, #MDCNFG_DMCEN
 	str		r1, [r0]
 
-
-#else /* NEW_SDRAM_INIT */
-
-	/* configure the MEMCLKCFG register */
-	ldr		r1, =MEMCLKCFG
-	ldr		r2, =0x00010001
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[0] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG0
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[1] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG1
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set MSC 0 register for SRAM memory */
-	ldr		r1, =MSC0
-	ldr		r2, =0x11191119
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[2] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG2
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[3] to VLIO mode */
-	ldr		r1, =CSADRCFG3
-	ldr		r2, =0x0032080B
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set MSC 1 register for VLIO memory */
-	ldr		r1, =MSC1
-	ldr		r2, =0x123C1119
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-#if 0
-	/* This does not work in Zylonite. -SC */
-	ldr		r0, =0x15fffff0
-	ldr		r1, =0xb10b
-	str		r1, [r0]
-	str		r1, [r0, #4]
-#endif
-
-	/* Configure ACCR Register */
-	ldr		r0, =ACCR		@ ACCR
-	ldr		r1, =0x0180b108
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Configure MDCNFG Register */
-	ldr		r0, =MDCNFG		@ MDCNFG
-	ldr		r1, =0x403
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Perform Resistive Compensation by configuring RCOMP register */
-	ldr		r1, =RCOMP		@ RCOMP
-	ldr		r2, =0x000000ff
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDMRS Register for SDCS0 */
-	ldr		r1, =MDMRS		@ MDMRS
-	ldr		r2, =0x60000023
-	ldr		r3, [r1]
-	orr		r2, r2, r3
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDMRS Register for SDCS1 */
-	ldr		r1, =MDMRS		@ MDMRS
-	ldr		r2, =0xa0000023
-	ldr		r3, [r1]
-	orr		r2, r2, r3
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDREFR */
-	ldr		r1, =MDREFR		@ MDREFR
-	ldr		r2, =0x00000006
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure EMPI */
-	ldr		r1, =EMPI		@ EMPI
-	ldr		r2, =0x80000000
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Hardware DDR Read-Strobe Delay Calibration */
-	ldr		r0, =DDR_HCAL		@ DDR_HCAL
-	ldr		r1, =0x803ffc07	    @ the offset is correct? -SC
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]
-
-	/* Here we assume the hardware calibration alwasy be successful. -SC */
-	/* Set DMCEN bit in MDCNFG Register */
-	ldr		r0, =MDCNFG		@ MDCNFG
-	ldr		r1, [r0]
-	orr		r1, r1, #0x40000000	@ enable SDRAM for Normal Access
-	str		r1, [r0]
-
-#endif /* NEW_SDRAM_INIT */
-
 #ifndef CFG_SKIP_DRAM_SCRUB
 	/* scrub/init SDRAM if enabled/present */
 	ldr	r8, =CFG_DRAM_BASE	/* base address of SDRAM (CFG_DRAM_BASE) */
@@ -290,96 +143,4 @@
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
 
 endlowlevel_init:
-
 	mov	pc, lr
-
-
-/*
-@********************************************************************************
-@ DDR calibration
-@
-@  This function is used to calibrate DQS delay lines.
-@ Monahans supports three ways to do it. One is software
-@ calibration. Two is hardware calibration. Three is hybrid
-@ calibration.
-@
-@ TBD
-@ -SC
-ddr_calibration:
-
-	@ Case 1:	Write the correct delay value once
-	@ Configure DDR_SCAL Register
-	ldr		r0, =DDR_SCAL		@ DDR_SCAL
-q	ldr		r1, =0xaf2f2f2f
-	str		r1, [r0]
-	ldr		r1, [r0]
-*/
-/*	@ Case 2:	Software Calibration
-	@ Write test pattern to memory
-	ldr		r5, =0x0faf0faf		@ Data Pattern
-	ldr		r4, =0xa0000000		@ DDR ram
-	str		r5, [r4]
-
-	mov		r1, =0x0		@ delay count
-	mov		r6, =0x0
-	mov		r7, =0x0
-ddr_loop1:
-	add		r1, r1, =0x1
-	cmp		r1, =0xf
-	ble		end_loop
-	mov		r3, r1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-	str		r3, [r2]
-
-	ldr		r2, [r4]
-	cmp		r2, r5
-	bne		ddr_loop1
-	mov		r6, r1
-ddr_loop2:
-	add		r1, r1, =0x1
-	cmp		r1, =0xf
-	ble		end_loop
-	mov		r3, r1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-	str		r3, [r2]
-
-	ldr		r2, [r4]
-	cmp		r2, r5
-	be		ddr_loop2
-	mov		r7, r2
-
-	add		r3, r6, r7
-	lsr		r3, r3, =0x1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-
-end_loop:
-
-	@ Case 3:	Hardware Calibratoin
-	ldr		r0, =DDR_HCAL		@ DDR_HCAL
-	ldr		r1, =0x803ffc07	    @ the offset is correct? -SC
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]
-	mov		pc, lr
-*/
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 50def59..c332f71 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -293,11 +293,6 @@
 {
 	unsigned long ndsr=0, event=0;
 
-	/* mk@tbd set appropriate timeouts */
-	/* 	if (state == FL_ERASING) */
-	/* 		timeo = CFG_HZ * 400; */
-	/* 	else */
-	/* 		timeo = CFG_HZ * 20; */
 	if(state == FL_WRITING) {
 		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
 	} else if(state == FL_ERASING) {
@@ -563,13 +558,12 @@
 
 
 	/* wait 10 us due to cmd buffer clear reset */
-	/* 	wait(10); */
+	/*	wait(10); */
 
 
 	nand->hwcontrol = dfc_hwcontrol;
-/* 	nand->dev_ready = dfc_device_ready; */
+/*	nand->dev_ready = dfc_device_ready; */
 	nand->eccmode = NAND_ECC_SOFT;
-	nand->chip_delay = NAND_DELAY_US;
 	nand->options = NAND_BUSWIDTH_16;
 	nand->waitfunc = dfc_wait;
 	nand->read_byte = dfc_read_byte;
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 83ae5e3..a92a450 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -821,21 +821,21 @@
 #define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
 #define RTSR		__REG(0x40900008)  /* RTC Status Register */
 #define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
-#define RDAR1	   __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2	   __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1	   __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2	   __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1	   __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
-#define SWAR2	   __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
-#define PIAR	   __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-#define RDCR	   __REG(0x40900010)  /* RTC Day Count Register. */
-#define RYCR	   __REG(0x40900014)  /* RTC Year Count Register. */
-#define SWCR	   __REG(0x40900028)  /* Stopwatch Count Register */
-#define RTCPICR	   __REG(0x40900034)  /* Periodic Interrupt Counter Register */
+#define RDAR1		__REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2		__REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1		__REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2		__REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1		__REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
+#define SWAR2		__REG(0x40900030)  /* Stopwatch Alarm Register 2 */
+#define PIAR		__REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+#define RDCR		__REG(0x40900010)  /* RTC Day Count Register. */
+#define RYCR		__REG(0x40900014)  /* RTC Year Count Register. */
+#define SWCR		__REG(0x40900028)  /* Stopwatch Count Register */
+#define RTCPICR		__REG(0x40900034)  /* Periodic Interrupt Counter Register */
 
-#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */
-#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */
-#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */
+#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
+#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
 #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
 #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
@@ -921,9 +921,10 @@
 
 #ifdef CONFIG_CPU_MONAHANS
 #define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers */
-/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
- * merged if GPIO Stuff is same too. */
+/* Missing: 32 Interrupt priority registers
+ * These are the same as beneath for PXA27x: maybe can be merged if
+ * GPIO Stuff is same too. 
+ */
 #define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
 #define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
@@ -983,24 +984,24 @@
 #define GCDR3		__REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
 
 #define GSRER0		__REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1  	__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER1		__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
 #define GSRER2		__REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3  	__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+#define GSRER3		__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
 
 #define GCRER0		__REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1  	__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER1		__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
 #define GCRER2		__REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3  	__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+#define GCRER3		__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
 
 #define GSFER0		__REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1  	__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER1		__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
 #define GSFER2		__REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3  	__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+#define GSFER3		__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
 
 #define GCFER0		__REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1  	__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER1		__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
 #define GCFER2		__REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3  	__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+#define GCFER3		__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
 
 #define GSDR(x)		__REG2(0x40E00400, ((x) & 0x60) >> 3)
 #define GCDR(x)		__REG2(0x40300420, ((x) & 0x60) >> 3)
@@ -1488,8 +1489,8 @@
 #define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
 #define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
 
-#define GPIO117_SCL	     (117 | GPIO_ALT_FN_1_OUT)
-#define GPIO118_SDA	     (118 | GPIO_ALT_FN_1_OUT)
+#define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
 
 /*
  * Power Manager
@@ -1709,10 +1710,10 @@
 #define ACCR_13MEND2	(1 << 21)
 #define ACCR_PCCE	(1 << 11)
 
-#define CKENA_30_MSL0	(1 << 30) 	/* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4	(1 << 29) 	/* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3	(1 << 28) 	/* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2	(1 << 27)  	/* SSP1 Unit Clock Enable */
+#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
 #define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
 #define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
 #define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
@@ -1720,27 +1721,27 @@
 #define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
 #define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
 #define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
-#define CKENA_19_TPM	(1 << 19) 	/* TPM Unit Clock Enable */
-#define CKENA_18_USIM1	(1 << 18) 	/* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0	(1 << 17) 	/* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR	(1 << 15) 	/* Consumer IR Clock Enable */
-#define CKENA_14_KEY	(1 << 14) 	/* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1	(1 << 13) 	/* MMC1 Clock Enable */
-#define CKENA_12_MMC0	(1 << 12) 	/* MMC0 Clock Enable */
-#define CKENA_11_FLASH	(1 << 11) 	/* Boot ROM Clock Enable */
-#define CKENA_10_SRAM	(1 << 10) 	/* SRAM Controller Clock Enable */
-#define CKENA_9_SMC	(1 << 9) 	/* Static Memory Controller */
-#define CKENA_8_DMC	(1 << 8) 	/* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7) 	/* 2D Graphics Clock Enable */
+#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
+#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
+#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
+#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
+#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
+#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
+#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
+#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
 #define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
-#define CKENA_4_NAND	(1 << 4) 	/* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA	(1 << 3) 	/* Camera Interface Clock Enable */
+#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
 #define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
 #define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
 
 #define CKENB_8_1WIRE	((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO	((1 << 7) + 32) 	/* GPIO Clock Enable */
-#define CKENB_6_IRQ	((1 << 6) + 32) 	/* Interrupt Controller Clock Enable */
+#define CKENB_7_GPIO	((1 << 7) + 32)	/* GPIO Clock Enable */
+#define CKENB_6_IRQ	((1 << 6) + 32)	/* Interrupt Controller Clock Enable */
 #define CKENB_4_I2C	((1 << 4) + 32)	/* I2C Unit Clock Enable */
 #define CKENB_1_PWM1	((1 << 1) + 32)	/* PWM2 & PWM3 Clock Enable */
 #define CKENB_0_PWM0	((1 << 0) + 32)	/* PWM0 & PWM1 Clock Enable */
@@ -2382,16 +2383,16 @@
 #define KPAS_SO		(0x1 << 31)
 #define KPASMKPx_SO	(0x1 << 31)
 
-#define GPIO113_BIT	   (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR	   __REG(0x40F00034)
-#define PSTR	   __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
-#define PSNR	   __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
-#define PVCR	   __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
-#define PKWR	   __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR	   __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4	    __REG(0x40A00080)  /* */
-#define OSCR4	    __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4	    __REG(0x40A000C0)  /* */
+#define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR		__REG(0x40F00034)
+#define PSTR		__REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
+#define PSNR		__REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
+#define PVCR		__REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
+#define PKWR		__REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR		__REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4		__REG(0x40A00080)  /* */
+#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4		__REG(0x40A000C0)  /* */
 
 #endif	/* CONFIG_PXA27X */
 
diff --git a/include/configs/delta.h b/include/configs/delta.h
index f230b03..cb002f7 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -62,7 +62,7 @@
 /*
  * select serial console configuration
  */
-#define CONFIG_FFUART	       1
+#define CONFIG_FFUART		1
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -168,8 +168,6 @@
 
 #define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define SECTORSIZE 		512
-#define NAND_DELAY_US		25	/* mk@tbd: could be 0, I guess */
 
 /* nand timeout values */
 #define CFG_NAND_PROG_ERASE_TO	3000
@@ -178,16 +176,15 @@
 #undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
 
 /* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH 	10
-#define NAND_TIMING_tCS 	0
+#define NAND_TIMING_tCH		10
+#define NAND_TIMING_tCS		0
 #define NAND_TIMING_tWH		20
-#define NAND_TIMING_tWP 	40
+#define NAND_TIMING_tWP		40
 
-#define NAND_TIMING_tRH 	20
-#define NAND_TIMING_tRP 	40
+#define NAND_TIMING_tRH		20
+#define NAND_TIMING_tRP		40
 
-#define NAND_TIMING_tR  	11123
-/* #define NAND_TIMING_tWHR	110 */
+#define NAND_TIMING_tR		11123
 #define NAND_TIMING_tWHR	100
 #define NAND_TIMING_tAR		10
 
@@ -199,87 +196,16 @@
 #define CONFIG_MTD_DEBUG
 #define CONFIG_MTD_DEBUG_VERBOSE 1
 
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
 
 #define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
 
-#define CFG_NO_FLASH	1
-#ifndef CGF_NO_FLASH
-/* these are required by the environment code */
-#define PHYS_FLASH_1            CFG_NAND0_BASE /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE         0x04000000 /* 64 MB */
-#define PHYS_FLASH_BANK_SIZE    0x04000000 /* 64 MB Banks */
-#define PHYS_FLASH_SECT_SIZE    (SECTORSIZE*1024) /*  KB sectors (x2) */
-#endif
+#define CFG_NO_FLASH		1
 
-/*
- * GPIO settings
- */
-#define CFG_GPSR0_VAL		0x00008000
-#define CFG_GPSR1_VAL		0x00FC0382
-#define CFG_GPSR2_VAL		0x0001FFFF
-#define CFG_GPCR0_VAL		0x00000000
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0x0060A800
-#define CFG_GPDR1_VAL		0x00FF0382
-#define CFG_GPDR2_VAL		0x0001C000
-#define CFG_GAFR0_L_VAL		0x98400000
-#define CFG_GAFR0_U_VAL		0x00002950
-#define CFG_GAFR1_L_VAL		0x000A9558
-#define CFG_GAFR1_U_VAL		0x0005AAAA
-#define CFG_GAFR2_L_VAL		0xA0000000
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL		0x23F223F2
-#define CFG_MSC1_VAL		0x3FF1A441
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x00018018
-#define CFG_MDMRS_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-#define _LED			0x08000010
-#define LED_BLANK		0x08000040
-
-/*
- * FLASH and environment organization
- */
-#ifndef CFG_NO_FLASH
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-
-/* NOTE: many default partitioning schemes assume the kernel starts at the
- * second sector, not an environment.  You have been warned!
- */
-#define	CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
-#endif /* #ifndef CFG_NO_FLASH */
-
-/* #define CFG_ENV_IS_NOWHERE */
 #define CFG_ENV_IS_IN_NAND	1
 #define CFG_ENV_OFFSET		0x40000
 #define CFG_ENV_OFFSET_REDUND	0x44000